公司简介
澜起科技
所属团队
职位属性
招聘类型：社招
工作性质：全职
职位描述
- Participate ASIC digital verification for memory buffer (DDR& LPDDR) projects;
- Create verification plans with designers;
- Develop ref-model and function coverage;
- Develop test sequence and test case, collect function/code coverage to 100%;
- Bug analysis/report/tracking;
任职条件
- Excellent team working style;
- Solid IP verification background;
- Mass production experiences on DDR/LPDDR protocol;
- Bachelor with 4+ years working experiences on ASIC digital verification;
- Production experiences on verification strategies and test plans;
- Familiar with System Verilog/UVM for test bench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Familiar with verification tools;
- Familiar with Linux, csh /Python or any script languages;
- Good English skills (read and write).