What you will do

• Digital back-end design for power management and signal processing IC products

• Digital system floorplan according to chip requirements

• Timing issue analysis and constraint improvement

• Synthesis, logic equivalence check, static timing analysis

• Place & route, timing sign-off, digital layout release

• DFT implementation and scan pattern generation

• Scripting of TCL, Make, etc. for implementation flow automation

• Technical documentations

What you will need

• BS degree with 8+ year or MS degree with 5+ year experience in digital back-end design

• Hand-on experience of place & route with timing/power/size optimization

• Hand-on experience of timing sign-off flow

• Good knowledge of RTL design

• Strong problem-solving skills

• Experience with either Cadence or Synopsys EDA tools

• Excellent communication and teamwork skills