What you will do

• Digital front-end design for power management and signal processing IC products

• Digital system definition and architecting according to product requirements

• RTL functional design and verification

• RTL checking of lint, clock domain crossing and reset domain crossing

• Timing constraint design and improvement

• Synthesis, logic equivalence check, static timing analysis

• Design optimization for timing closure and power/size saving

• DFT architecting and design

• Scripting of Perl. Python, etc. for design automation

• Technical documentation

What you will need

• BS degree with 8+ year or MS degree with 5+ year experience in digital front-end design

• Excellent Verilog or SystemVerilog RTL coding skill

• Hand-on experience of RTL design and function debugging in simulation

• Hand-on experience of timing/power/size analysis and optimization

• Strong problem-solving skills

• Experience with either Cadence or Synopsys EDA tools

• Excellent communication and teamwork skills