元夕 · 测试公司

模拟设计工程师

薪资面议  /  上海

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职位属性

招聘类型：社招
工作性质：全职

职位描述

  1. Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
  2. Oversee layout and verification activities which include floor plan, LVS and DRC.
  3. Support Product SerDes related issue trouble-shooting.


任职条件

  1. Bachelor degree or Master degree in ASIC Design Relevant;
  2. At least 3 years in RF/Analog IC design;
  3. Good fundamental in analysis and design of analog / mixed-signal circuits; Experience in Verilog, AHDL and/or Matlab; Ability to do layout and provide verification/debugging guidance; Solid knowledge of EDA design tools (Analog artist, spectre, HSPICE and nc-verilog ...); Familiar with Computer languages such as C, C++, perl;
  4. Experience in any of the following areas is preferred: PLL, high-speed I/O’s;
  5. Good communication skills and Good oral/written English.


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