元夕 · 测试公司
数字设计工程师
薪资面议 / 上海
元夕
"Driven by our purpose"
- Write Micro-Architecture and Design Spec;
- Write RTL coding of ASIC logic, monitor &debug logic, integration logic etc. for block or top level;
- Do IP level Lint /CDC check / synthesis / timing analysis / formality check/power analysis/optimize, understand some timing/power constraint & script;
- Assist on Verification Engineer to complete module to top level verification and debugging;
- Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes;
- Take silicon debugging of the related module functionalities.
- MSEE with 3+ year experience of digital design;
- Strong skills of logic design, simulation debug and ECO changes with netlist database;
- Hands on experience in EDA tools such as VCS, NC-sim, Spyglass, DC, PT, Equivalence check, PrimePower or PowerArtist etc.;
- Basic skills of script and be familiar with Perl, Python, Tcl, etc.;
- Self-motivated, good team work spirit and communication skills;
- Following working Knowledge and experiences will be one advantage;
- (1) Experience in high-speed IO design (Ethernet, PCIe, USB3/4, SATA, etc);
- (2) Experience in CPU or SOC design;
- (3) Experience in logic’s PPA optimize
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Social Insurance
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Annual Paid Leave up to 20 days
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Health Care Insurance
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Unemployment Insurance
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Maternity Insurance
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Business Health Care Insurance
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Pension Insurance
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Occupational Injury Insurance
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Management Trainee Program
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1on1 Career Development Coach
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入职快
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六险一金
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不加班
