元夕 · 测试公司

模拟设计工程师

薪资面议  /  上海

昨天 15:22 更新

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职位属性

招聘类型:社招
工作性质:全职

职位描述

JOB DESCRIPTION:

  1. Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
  2. Oversee layout and verification activities which include floor plan, LVS and DRC.

QUALIFICATIONS:

  1. Bachelor degree or Master degree in ASIC Design Relevant;
  2. At least 3 years in RF/Analog IC design;
  3. Good fundamental in analysis and design of analog / mixed-signal circuits; Experience in Verilog, AHDL and/or Matlab; Ability to do layout and provide verification/debugging guidance; Solid knowledge of EDA design tools (Analog artist, spectre, HSPICE and nc-verilog ...); Familiar with Computer languages such as C, C++, Python;
  4. Experience in any of the following areas is preferred: SerDes, DDR,Transmitter, Receiver, DDR IO interface, etc.;
  5. Good communication skills and Good oral/written English;
  6. Knowledge, experience and skills on high speed signal integrity field is a plus.


公司福利

  • Social Insurance
  • Annual Paid Leave up to 20 days
  • Health Care Insurance
  • Unemployment Insurance
  • Maternity Insurance
  • Business Health Care Insurance
  • Pension Insurance
  • Occupational Injury Insurance
  • Management Trainee Program
  • 1on1 Career Development Coach
  • 入职快
  • 六险一金
  • 不加班