JOB DESCRIPTION:

1. Write Micro-Architecture and Design Spec;
2. Write RTL coding of ASIC logic, monitor &debug logic, integration logic etc. for block or top level;
3. Do IP level Lint /CDC check / synthesis / timing analysis / formality check/power analysis/optimize, understand some timing/power constraint & script;
4. Assist on Verification Engineer to complete module to top level verification and debugging;
5. Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes;
6. Take silicon debugging of the related module functionalities.

QUALIFICATIONS:

1. MSEE with 3+ year experience of digital design;
2. Strong skills of logic design, simulation debug and ECO changes with netlist database;
3. Hands on experience in EDA tools such as VCS, NC-sim, Spyglass, DC, PT, Equivalence check, PrimePower or PowerArtist etc.;
4. Basic skills of script and be familiar with Perl, Python, Tcl, etc.;
5. Self-motivated, good team work spirit and communication skills;
6. Following working Knowledge and experiences will be one advantage;
7. (1) Experience in high-speed IO design (Ethernet, PCIe, USB3/4, SATA, etc);
8. (2) Experience in CPU or SOC design;
9. (3) Experience in logic’s PPA optimize