About the role
The Layout Engineer is responsible for creating testkey layouts and pcell layouts in the semiconductor design process.
What you will do
•Design test key layouts and process monitoring patterns for CMOS/BCD technologies
•Perform DRC/LVS verification to ensure zero critical layout errors
•Support pre-tapeout validation (e.g., EM/IR analysis), execute some basic LOP tasks, and coordinate data delivery to foundries
•Collaborate with PDK engineers to develop Pcells for process design kits
What you will need
•Bachelor’s degree or higher in Electrical Engineering or related fields
•3+ years of semiconductor layout design experience, with preference for CMOS/BCD layout experience
•Proficiency in Smartcell, Tcmagic, Cadence Virtuoso, and Calibre tools
•Strong knowledge of the devices, ESD, mismatch and reliability test key layouts in CMOS/BCD process
Talent acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright
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D&I Statement
As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.
In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.
